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?2001 integrated device technology, inc. dsc-5621/3 1 ce 0r r/ w r ce 1r lb r ub r 128k x 18 memory array address decoder a 16r a 0r address decoder ce 0l r/ w l ce 1l lb l ub l dout0-8_l dout9-17_l dout0-8_r dout9-17_r b e 0 l b e 1 l b e 1 r b e 0 r i/o 0l -i/o 17l i/o 0r - i/o 17r din_l addr_l din_r addr_r oe r oe l arbitration interrupt semaphore logic sem l int l busy l m/ s r/ w l oe l r/ w r oe r busy r sem r int r ce 0l ce 1l ce 0r ce 1r tms tck trst tdi tdo jtag 5621 drw 01 a 16l a 0l
fully asynchronous operation from either port separate byte controls for multiplexed bus and bus matching compatibility supports jtag features compliant to ieee 1149.1 ? due to limited pin count, jtag is not supported on the 128-pin tqfp package. lvttl-compatible, single 3.3v (150mv) power supply for core lvttl-compatible, selectable 3.3v (150mv)/2.5v (100mv) power supply for i/os and control signals on each port available in a 128-pin thin quad flatpack, 208-ball fine pitch ball grid array, and 256-ball ball grid array industrial temperature range (?40c to +85c) is available for selected speeds
true dual-port memory cells which allow simultaneous access of the same memory location high-speed access ? commercial: 10/12/15ns (max.) ? industrial: 12/15ns (max.) dual chip enables allow for depth expansion without external logic idt70v639 easily expands data bus width to 36 bits or more using the master/slave select when cascading more than one device m/ s = v ih for busy output flag on master, m/ s = v il for busy input on slave busy and interrupt flags on-chip port arbitration logic full on-chip hardware support of semaphore signaling between ports high-speed 3.3v 128k x 18 asynchronous dual-port static ram preliminary idt70v639s notes: 1. busy is an input as a slave (m/ s =v il ) and an output when it is a master (m/ s =v ih ). 2. busy and int are non-tri-state totem-pole outputs (push-pull).
idt70v639s preliminary high-speed 3.3v 128k x 18 asynchronous dual-port static ram industrial and commercial temperature ra nges 2 the idt70v639 is a high-speed 128k x 18 asynchronous dual-port static ram. the idt70v639 is designed to be used as a stand-alone 2304k-bit dual-port ram or as a combination master/slave dual- port ram for 36-bit-or-more word system. using the idt master/ slave dual-port ram approach in 36-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. this device provides two independent ports with separate control, address, and i/o pins that permit independent, asynchronous access for reads or writes to any location in memory. an automatic power down feature controlled by the chip enables (either ce 0 or ce 1 ) permit the on-chip circuitry of each port to enter a very low standby power mode. the 70v639 can support an operating voltage of either 3.3v or 2.5v on one or both ports, controlled by the opt pins. the power supply for the core of the device (v dd ) remains at 3.3v.
!" notes: 1. all v dd pins must be connected to 3.3v power supply. 2. all v ddq pins must be connected to appropriate power supply: 3.3v if opt pin for that port is set to v ih (3.3v) and 2.5v if opt pin for that port is set to v il (0v). 3. all v ss pins must be connected to ground. 4. package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch. 5. this package code is used to reference the package diagram. 6. this text does not indicate orientation of the actual part-marking. 17 16 15 14 12 13 10 9 8 7 6 5 4 3 2 1 11 a b c d e f g h j k l m n p r t u i/o 9l nc v ss a 4l int l sem l nc a 8l a 12l a 16l v ss nc opt l a 0l nc v ss nc nc a 1l a 5l busy l v ss ce 0l ce 1l nc a 9l a 13l nc i/o 8l v ddqr v ss v ddql i/o 9r v ddqr v dd a 2l a 6 l r/ w l v ss ub l a 10l a 14l nc nc i/o 8r v dd i/o 11l v ss i/o 10l nc v dd a 3l nc oe l nc i/o 11r v ddqr i/o 10r v ddql nc nc v ss nc v ss i/o 12l nc v dd nc v ddqr i/o 12r v ddql v dd v ss v ss nc i/o 14l v ddqr v ddql nc i/o 15 r v ss i/o 7r v ddql i/o 7l a 15l a 11l a 7l lb l i/o 6l nc v ss nc v ss i/o 6r nc nc v dd q l i/o 5l nc v dd nc v ss i/o 5r v ss v dd q r i/o 3r v ddql i/o 4r v ss i/o 4l v ss i/o 3l nc a 0r a 1r a 2r a 3r a 4r a 5r a 6r i/o 1r nc v ss nc i/o 15l a 16r a 12r a 8r nc v dd sem r int r v ddqr nc i/o 1l nc v ss nc i/o 17r nc a 13r a 9r nc ce 0r ce 1r v dd v ss busy r v ss v dd v ss v ddql i/o 0r v ddqr nc i/o 17l v ddql nc nc a 14r a 10r ub r v ss nc nc v ss i/o 2r nc v ss nc v dd a 15r a 11r a 7r lb r oe r m/ s r/ w r v ddql i/o 2l opt r nc i/o 0l 70v639bf bf-208 (5) 208-ball bga top view (6) 5621 tbl 02b i/o 13l i/o 14r v ss i/o 13r v ss i/o 16r i/o 16l v ddqr nc a b c d e f g h j k l m n p r t u v ss nc nc v ddqr v ss v dd v ss nc v dd v dd tdo tdi tck tms trst v ss
idt70v639s preliminary high-speed 3.3v 128k x 18 asynchronous dual-port static ram industrial and commercial temperature ra nges 3 notes: 1. all v dd pins must be connected to 3.3v power supply. 2. all v ddq pins must be connected to appropriate power supply: 3.3v if opt pin for that port is set to v ih (3.3v) and 2.5v if opt pin for that port is set to v il (0v). 3. all v ss pins must be connected to ground. 4. package body is approximately 14mm x 20mm x 1.4mm. 5. this package code is used to reference the package diagram. 6. this text does not indicate orientation of the actual part-marking. 7. due to the restricted number of pins, jtag is not supported in the pk-128 package. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 70 69 68 67 66 65 91 71 a 14l a 15l a 16l nc io 9l io 9r v ddql v ss io 10l io 10r v ddqr v ss io 11l io 11r io 12l io 12r v dd v dd v ss v ss io 13r io 13l io 14r io 14l io 15r io 15l v ddql v ss io 16r io 16l v ddqr v ss io 17r io 17l nc a 16r a 15r a 14r a 1r a 0r opt r io 0l io 0r v ddqr v ss io 1l io 1r v ddql v ss io 2l io 2r io 3l io 3r io 4l io 4r v ss v ss v dd v dd io 5l io 5r v ddqr v ss io 7r io 7l v ddql v ss nc io 8r io 8l v ss opt l a 0l a 1l io 6r io 6l 70v639prf pk-128 (5) 128-pin tqfp top view (6) 5621 drw 02a a 1 3 l a 1 2 l a 1 1 l a 1 0 l a 9 l a 8 l a 7 l u b l l b l c e 1 l c e 0 l v d d v d d v s s v s s s e m l o e l r / w l b u s y l i n t l n c a 6 l a 5 l a 4 l a 3 l a 2 l a 1 3 r a 1 2 r a 1 1 r a 1 0 r a 9 r a 8 r a 7 r u b r l b r c e 1 r c e 0 r v d d v d d v s s v s s s e m r o e r r / w r b u s y r i n t r m / s a 6 r a 5 r a 4 r a 3 r a 2 r 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 1 2 8 1 2 7 1 2 6 1 2 5 1 2 4 1 2 3 1 2 2 1 2 1 1 2 0 1 1 9 1 1 8 1 1 7 1 1 6 1 1 5 1 1 4 1 1 3 1 1 2 1 1 1 1 1 0 1 0 9 1 0 8 1 0 7 1 0 6 1 0 5 1 0 4 1 0 3 .
!#" $ %"
idt70v639s preliminary high-speed 3.3v 128k x 18 asynchronous dual-port static ram industrial and commercial temperature ra nges 4
!" $ %" notes: 1. all v dd pins must be connected to 3.3v power supply. 2. all v ddq pins must be connected to appropriate power supply: 3.3v if opt pin for that port is set to v ih (3.3v), and 2.5v if opt pin for that port is set to v il (0v). 3. all v ss pins must be connected to ground supply. 4. package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch. 5. this package code is used to reference the package diagram. 6. this text does not indicate orientation of the actual part-marking. 70v639bc bc-256 (5) 256-pin bga top view (6) e16 i/o 7r d16 i/o 8r c16 i/o 8l b16 nc a16 nc a15 nc b15 nc c15 nc d15 nc e15 i/o 7l e14 nc d14 nc d13 v dd c12 a 6l c14 opt l b14 nc a14 a 0l a12 a 5l b12 a 4l c11 busy l d12 v ddqr d11 v ddqr c10 sem l b11 nc a11 int l d8 v ddqr c8 nc a9 ce 1l d9 v ddql c9 lb l b9 ce 0l d10 v ddql c7 a 7l b8 ub l a8 nc b13 a 1l a13 a 2l a10 oe l d7 v ddqr b7 a 9l a7 a 8l b6 a 12l c6 a 10l d6 v ddql a5 a 14l b5 a 15l c5 a 13l d5 v ddql a4 nc b4 nc c4 a 16l d4 v dd a3 nc b3 tdo c3 v ss d3 nc d2 i/o 9r c2 i/o 9l b2 nc a2 tdi a1 nc b1 nc c1 nc d1 nc e1 i/o 10r e2 i/o 10l e3 nc e4 v ddql f1 i/o 11l f2 nc f3 i/o 11r f4 v ddql g1 nc g2 nc g3 i/o 12l g4 v ddqr h1 nc h2 i/o 12r h3 nc h4 v ddqr j1 i/o 13l j2 i/o 14r j3 i/o 13r j4 v ddql k1 nc k2 nc k3 i/o 14l k4 v ddql l1 i/o 15l l2 nc l3 i/o 15r l4 v ddqr m1 i/o 16r m2 i/o 16l m3 nc m4 v ddqr n1 nc n2 i/o 17r n3 nc n4 v dd p1 nc p2 i/o 17l p3 tms p4 a 16r r1 nc r2 nc r3 trst r4 nc t1 nc t2 tck t3 nc t4 nc p5 a 13r r5 a 15r p12 a 6r p8 nc p9 lb r r8 ub r t8 nc p10 sem r t11 int r p11 busy r r12 a 4r t12 a 5r p13 a 3r p7 a 7r r13 a 1r t13 a 2r r6 a 12r t5 a 14r t14 a 0r r14 opt r p14 nc p15 nc r15 nc t15 nc t16 nc r16 nc p16 i/o 0l n16 nc n15 i/o 0r n14 nc m16 nc m15 i/o 1l m14 i/o 1r l16 i/o 2r l15 nc l14 i/o 2l k16 i/o 3l k15 nc k14 nc j16 i/o 4l j15 i/o 3r j14 i/o 4r h16 i/o 5r h15 nc h14 nc g16 nc g15 nc g14 i/o 5l f16 i/o 6l f14 i/o 6r f15 nc r9 ce 0r r11 m/ s t6 a 11r t9 ce 1r a6 a 11l b10 r/ w l c13 a 3l p6 a 10r r10 r/ w r r7 a 9r t10 oe r t7 a 8r , e5 v dd e6 v dd e7 v ss e8 v ss e9 v ss e10 v ss e11 v dd e12 v dd e13 v ddqr f5 v dd f6 v ss f8 v ss f9 v ss f10 v ss f12 v dd f13 v ddqr g5 v ss g6 v ss g7 v ss g8 v ss g9 v ss g10 v ss g11 v ss g12 v ss g13 v ddql h5 v ss h6 v ss h7 v ss h8 v ss h9 v ss h10 v ss h11 v ss h12 v ss h13 v ddql j5 v ss j6 v ss j7 v ss j8 v ss j9 v ss j10 v ss j11 v ss j12 v ss j13 v ddqr k5 v ss k6 v ss k7 v ss k8 v ss l5 v dd l6 v ss l7 v ss l8 v ss m5 v dd m6 v dd m7 v ss m8 v ss n5 v ddqr n6 v ddqr n7 v ddql n8 v ddql k9 v ss k10 v ss k11 v ss k12 v ss l9 v ss l10 v ss l11 v ss l12 v dd m9 v ss m10 v ss m11 v dd m12 v dd n9 v ddqr n10 v ddqr n11 v ddql n12 v ddql k13 v ddqr l13 v ddql m13 v ddql n13 v dd f7 v ss f11 v ss 5621 drw 02c ,
idt70v639s preliminary high-speed 3.3v 128k x 18 asynchronous dual-port static ram industrial and commercial temperature ra nges 5 notes: 1. v dd , opt x , and v ddqx must be set to appropriate operating levels prior to applying inputs on i/o x . 2. opt x selects the operating voltage levels for the i/os and controls on that port. if opt x is set to v ih (3.3v), then that port's i/os and controls will operate at 3.3v levels and v ddqx must be supplied at 3.3v. if opt x is set to v il (0v), then that port's i/os and controls will operate at 2.5v levels and v ddqx must be supplied at 2.5v. the opt pins are independent of one another?both ports can operate at 3.3v levels, both can operate at 2.5v levels, or either can operate at 3.3v with the other at 2.5v. left port right port names ce 0l , ce 1l ce 0r , ce 1r chip enables r/ w l r/ w r read/write enable oe l oe r output enable a 0l - a 16 l a 0r - a 16r address i/o 0l - i/o 17 l i/o 0r - i/o 17r data input/outp ut sem l sem r semaphore enable int l int r inte rrup t flag busy l busy r busy flag ub l ub r upper byte select lb l lb r lower byte select v dd q l v ddqr power (i/o bus) (3.3v or 2.5v) (1 ) opt l opt r op tio n fo r se le cting v ddqx (1,2) m/ s master or slave select v dd power (3.3v) (1 ) v ss ground (0v) tdi test data inp ut tdo test data outp ut tck test logic clock (10mhz) tms test mode select trst reset (initialize tap controller) 56 21 tbl 01
idt70v639s preliminary high-speed 3.3v 128k x 18 asynchronous dual-port static ram industrial and commercial temperature ra nges 6 note: 1. "h" = v ih, "l" = v il, "x" = don't care. &
'&()*+,-. ,( " oe sem ce 0 ce 1 ub lb r/ w byte 1 i/o 9-1 7 byte 0 i/o 0-8 mode x h h x x x x high-z high-z deselected ? power down x h x l x x x high-z high-z deselected ? power down x h l h h h x high-z high-z both bytes deselected xhlhhll high-z d in write to by te 0 only xhlhlhl d in high-z write to byte 1 only xhlhlll d in d in write to both bytes lhlhhlh high-z d out read byte 0 only lhlhlhh d out high-z read byte 1 only lhlhllh d out d out read both bytes h h l h l l x high-z high-z outputs disabled 5621 tbl 02 &
'&())/0'+,-. " note: 1. there are eight semaphore flags written to i/o 0 and read from all the i/os (i/o 0 -i/o 17 ). these eight semaphore flags are addressed by a 0 -a 2 . 2. ce = l occurs when ce 0 = v il and ce 1 = v ih . 3. each byte is controlled by the respective ub or lb . to read data ub and/or lb = v il . inputs (1 ) outputs mode ce (2 ) r/ w oe ub lb sem i/o 1-1 7 i/o 0 hhlllldata out data out read data in semaphore flag (3) h xx l l x data in write i/o 0 into semaphore flag lxxxxl ______ ______ not allowed 5621 tbl 03
idt70v639s preliminary high-speed 3.3v 128k x 18 asynchronous dual-port static ram industrial and commercial temperature ra nges 7 +,,1 &
,0
23 " +,,1 , 4 '3 5 %63 7(
89
+ " notes: 1. v il > -1.5v for pulse width less than 10 ns. 2. v term must not exceed v ddq + 100mv. 3. to select operation at 2.5v levels on the i/os and controls of a given port, the opt pin for that port must be set to v il (0v), and v ddqx for that port must be supplied as indicated above. notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed v dd + 150mv for more than 25% of the cycle time or 4ns maximum, and is limited to < 20ma for the period of v term > v dd + 150mv. note: 1. this is the parameter t a . this is the "instant on" case temperature. +,,1 , 4 '3 5 % 3 notes: 1. v il > -1.5v for pulse width less than 10 ns. 2. v term must not exceed v ddq + 150mv. 3. to select operation at 3.3v levels on the i/os and controls of a given port, the opt pin for that port must be set to v ih (3.3v), and v ddqx for that port must be supplied as indicated above. grade ambient temperature gnd v dd commercial 0 o c to +70 o c0v3.3v + 150mv industrial -40 o c to +85 o c0v3.3v + 150mv 5621 tbl 04 symbol rating commercial & industrial unit v te r m (2 ) terminal voltage with respect to gnd -0.5 to +4.6 v t bias temperature under bias -55 to +125 o c t stg storage temperature -65 to +150 o c i out dc output current 50 ma 5621 tbl 05 symbol parameter min. typ. max. unit v dd core supply voltage 3.15 3.3 3.45 v v ddq i/o supply voltage (3) 2.4 2.5 2.6 v v ss ground 0 0 0 v v ih input high voltage (3) (address & control inputs) 1.7 ____ v ddq + 100mv (2) v v ih input high voltage - i/o (3) 1.7 ____ v ddq + 100mv (2) v v il input low voltage -0.5 (1) ____ 0.7 v 5621 tbl 06 symbol parameter min. typ. max. unit v dd core supply voltage 3.15 3.3 3.45 v v ddq i/o supply voltage (3) 3.15 3.3 3.45 v v ss ground 0 0 0 v v ih inp ut high voltage (address & control inputs) (3) 2.0 ____ v ddq + 150mv (2) v v ih inp ut high voltage - i/o (3) 2.0 ____ v ddq + 150mv (2) v v il input low voltage -0.3 (1) ____ 0.8 v 5621 tbl 07 notes: 1. these parameters are determined by device characterization, but are not production tested. 2. 3dv references the interpolated capacitance when the input and output switch from 0v to 3v or from 3v to 0v. 3. c out also references c i/o . " & 7 :;6< :%8= > "&5 1?@ symbol parameter conditions (2 ) max. unit c in input capacitance v in = 3dv 8 pf c out (3 ) output capacitance v out = 3dv 10.5 pf 5621 tbl 08
idt70v639s preliminary high-speed 3.3v 128k x 18 asynchronous dual-port static ram industrial and commercial temperature ra nges 8 ' 1a '1 &
,0
23 + 3 : % 3b63" note: 1. at v dd < - 2.0v input leakages are undefined. 2. v ddq is selectable (3.3v/2.5v) via opt pins. refer to p.5 for details. symbol parameter test conditions 70v639s unit min. max. |i li | input leakage current (1 ) v ddq = max., v in = 0v to v ddq ___ 10 a |i lo | output leakage current ce 0 = v ih or ce 1 = v il , v out = 0v to v ddq ___ 10 a v ol (3.3v) output low voltage (2 ) i ol = +4ma, v ddq = min. ___ 0.4 v v oh (3.3v) output high voltage (2 ) i oh = -4ma, v ddq = min. 2.4 ___ v v ol (2.5v) output low voltage (2 ) i ol = +2ma, v ddq = min. ___ 0.4 v v oh (2.5v) output high voltage (2 ) i oh = -2ma, v ddq = min. 2.0 ___ v 5621 tbl 09 ' 1a '1 &
,0
23 + " 3 : % 3b63" notes: 1. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency read cycle of 1/t rc , using "ac test conditions" at input levels of gnd to 3v. 2. f = 0 means no address or control lines change. applies only to input at cmos level standby. 3. port "a" may be either left or right port. port "b" is the opposite from port "a". 4. v dd = 3.3v, t a = 25 c for typ, and are not production tested. i dd dc (f=0) = 120ma (typ). 5. ce x = v il means ce 0x = v il and ce 1x = v ih ce x = v ih means ce 0x = v ih or ce 1x = v il ce x < 0.2v means ce 0x < 0.2v and ce 1x > v cc - 0.2v ce x > v cc - 0.2v means ce 0x > v cc - 0.2v or ce 1x - 0.2v "x" represents "l" for left port or "r" for right port. 70v639s10 com'l only 70v639s12 com'l & ind 70v639s15 com'l & ind symbol parameter test condition version typ. (4 ) max. typ. (4 ) max. typ. (4 ) max. unit i dd dynamic operating current (both ports active) ce l and ce r = v il , outputs disabled, f = f max (1 ) com'l s 340 500 315 465 300 440 ma ind s ____ ____ 365 515 350 490 i sb1 standby current (both ports - ttl level inputs) ce l = ce r = v ih f = f max (1 ) com'l s 115 165 90 125 75 100 ma ind s ____ ____ 115 150 100 125 i sb2 standby current (one port - ttl level inputs) ce "a" = v il and ce "b" = v ih (5 ) active port outputs disabled, f=f max (1 ) com'l s 225 340 200 325 175 315 ma ind s ____ ____ 225 365 200 350 i sb3 full standby current (both ports - cmos level inputs) both ports ce l and ce r > v dd - 0.2v, v in > v dd - 0.2v or v in < 0.2v, f = 0 (2 ) com'ls315315315 ma ind s ____ ____ 615615 i sb4 full standby current (one port - cmos level inputs) ce "a" < 0.2v and ce "b" > v dd - 0.2v (5 ) v in > v dd - 0.2v or v in < 0.2v, active port, outputs disabled, f = f max (1 ) com'l s 220 335 195 320 170 310 ma ind s ____ ____ 220 360 195 345 5621 tbl 1 0
idt70v639s preliminary high-speed 3.3v 128k x 18 asynchronous dual-port static ram industrial and commercial temperature ra nges 9 7& , 3 5 c % 3-%63" figure 1. ac output test load. figure 2. output test load (for t cklz , t ckhz , t olz , and t ohz ). *including scope and jig. figure 3. typical output derating (lumped capacitive load). input pulse levels input rise/fall times input timing reference levels output reference levels output load gnd to 3.0v / gnd to 2.5v 2ns max. 1.5v/1.25v 1.5v1.25v figures 1 and 2 5621 tbl 11 1.5v/1.25 50 ? 50 ? 5621 drw 03 10pf (tester) data out , 5621 drw 04 590 ? 5pf* 435 ? 3.3v data out , 833 ? 5pf* 770 ? 2.5v data out , -1 1 2 3 4 5 6 7 20.5 30 50 80 100 200 10.5pf is the i/o capacitance of this device, and 10pf is the ac test load capacitance. capacitance (pf) ? taa (typical, ns) 5621 drw 05 ? ? ? ? , figure 2. output test load
idt70v639s preliminary high-speed 3.3v 128k x 18 asynchronous dual-port static ram industrial and commercial temperature ra nges 10 7 ' 1a ' 1 &
,0
23 + 6" notes: 1. transition is measured 0mv from low or high-impedance voltage with output test load (figure 2). 2. this parameter is guaranted by device characterization, but is not production tested. 3. to access ram, ce = v il and sem = v ih . to access semaphore, ce = v ih and sem = v il . either condition must be valid for the entire t ew time. 4. the specification for t dh must be met by the device supplying write data to the ram under all operating conditions. although t dh and t ow values will vary over voltage and temperature, the actual t dh will always be smaller than the actual t ow . 5. these values are valid regardless of the power supply level selected for i/o and control signals (3.3v/2.5v). see page 5 for details. 7 ' 1a ' 1 &
,0
23 6" symbol parameter 70v639s10 com'l only 70v639s12 com'l & ind 70v639s15 com'l & ind unit min. max. min. max. min. max. read cycle t rc read cycle time 10 ____ 12 ____ 15 ____ ns t aa address access time ____ 10 ____ 12 ____ 15 ns t ace chip enable access time (3) ____ 10 ____ 12 ____ 15 ns t abe byte enable access time (3) ____ 5 ____ 6 ____ 7ns t aoe output enable access time ____ 5 ____ 6 ____ 7ns t oh output hold from address change 3 ____ 3 ____ 3 ____ ns t lz output low-z time (1,2) 0 ____ 0 ____ 0 ____ ns t hz output high-z time (1,2) 040608ns t pu chip en able to power up time (2) 0 ____ 0 ____ 0 ____ ns t pd chip disab le to power down time (2) ____ 10 ____ 10 ____ 15 ns t sop semaphore flag update pulse ( oe or sem ) ____ 4 ____ 6 ____ 8ns t saa semaphore address access time 3 10 3 12 3 20 ns 5621 tbl 1 2 symbol parameter 70v639s10 com'l only 70v639s12 com'l & ind 70v639s15 com'l & ind unit min. max. min. max. min. max. wri te cycl e t wc write cycle time 10 ____ 12 ____ 15 ____ ns t ew chip enable to end-of-write (3) 8 ____ 10 ____ 12 ____ ns t aw address valid to end-of-write 8 ____ 10 ____ 12 ____ ns t as address set-up time (3) 0 ____ 0 ____ 0 ____ ns t wp write pulse width 8 ____ 10 ____ 12 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ ns t dw data valid to end-of-write 6 ____ 8 ____ 10 ____ ns t dh data ho ld time (4) 0 ____ 0 ____ 0 ____ ns t wz write en able to output in high-z (1,2) ____ 4 ____ 4 ____ 4ns t ow output active from end -of-write (1, 2,4) 0 ____ 0 ____ 0 ____ ns t swrd sem flag write to read time 5 ____ 5 ____ 5 ____ ns t sps sem flag contention window 5 ____ 5 ____ 5 ____ ns 5621 tbl 1 3
idt70v639s preliminary high-speed 3.3v 128k x 18 asynchronous dual-port static ram industrial and commercial temperature ra nges 11 &4c4c4 .a+,2 6" notes: 1. timing depends on which signal is asserted last, oe , ce , lb or ub . 2. timing depends on which signal is de-asserted first ce , oe , lb or ub . 3. t bdd delay is required only in cases where the opposite port is completing a write operation to the same address location. for simu ltaneous read operations busy has no relation to valid output data. 4. start of valid data depends on which timing becomes effective last t aoe , t ace , t aa or t bdd . 5. sem = v ih . t rc r/ w ce addr t aa oe ub , lb 5621 drw 06 (4) t ace (4) t aoe (4) t abe (4) (1) t lz t oh (2) t hz (3,4) t bdd data out busy out valid data (4) (6) ce 5621 drw 07 t pu i cc i sb t pd 50% 50% .
idt70v639s preliminary high-speed 3.3v 128k x 18 asynchronous dual-port static ram industrial and commercial temperature ra nges 12 &.a. 2%+- w ,& 6d" &.a. 2% ce ,& 6" notes: 1. r/ w or ce or be n = v ih during all address transitions. 2. a write occurs during the overlap (t ew or t wp ) of a ce = v il and a r/ w = v il for memory array writing cycle. 3. t wr is measured from the earlier of ce or r/ w (or sem or r/ w ) going high to the end of write cycle. 4. during this period, the i/o pins are in the output state and input signals must not be applied. 5. if the ce or sem = v il transition occurs simultaneously with or after the r/ w = v il transition, the outputs remain in the high-impedance state. 6. timing depends on which enable signal is asserted last, ce or r/ w . 7. this parameter is guaranteed by device characterization, but is not production tested. transition is measured 0mv from steady state with the output test load (figure 2). 8. if oe = v il during r/w controlled write cycle, the write pulse width must be the larger of t wp or (t wz + t dw ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe = v ih during an r/ w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp . 9. to access ram, ce = v il and sem = v ih . to access semaphore, ce = v ih and sem = v il . t ew must be met for either condition. r/ w t wc t hz t aw t wr t as t wp data out (2) t wz t dw t dh t ow oe address data in (6) (4) (4) (7) ub , lb 5621 drw 08 (9) ce or sem (9) (7) (3) 5621 drw 09 t wc t as t wr t dw t dh address data in r/ w t aw t ew ub , lb (3) (2) (6) ce or sem (9) (9)
idt70v639s preliminary high-speed 3.3v 128k x 18 asynchronous dual-port static ram industrial and commercial temperature ra nges 13 &.a0'+, . & '0, " notes: 1. d or = d ol = v il , ce l = ce r = v ih . refer also to truth table ii for appropriate ub / lb controls. 2. all timing is the same for left and right ports. port "a" may be either left or right port. "b" is the opposite from port "a" . 3. this parameter is measured from r/ w "a" or sem "a" going high to r/ w "b" or sem "b" going high. 4. if t sps is not satisfied,the semaphore will fall positively to one side or the other, but there is no guarantee which side will be gra nted the semaphore flag. &.a0'. !" notes: 1. ce = v ih or ub and lb = v ih for the duration of the above timing (both write and read cycle) (refer to chip enable truth table). refer also to truth table ii for appropriate ub / lb controls. 2. "data out valid" represents all i/o's (i/o 0 - i/o 17 ) equal to the semaphore value. sem / ub / lb (1) 5621 drw 10 t aw t ew i/o valid address t saa r/ w t wr t oh t ace valid address data valid in data out t dw t wp t dh t as t swrd t aoe read cycle write cycle a 0 -a 2 oe valid (2) t sop t sop sem "a" 5621 drw 11 t sps match r/ w "a" match a 0"a" -a 2"a" side "a" (2) sem "b" r/ w "b" a 0"b" -a 2"b" side "b" (2)
idt70v639s preliminary high-speed 3.3v 128k x 18 asynchronous dual-port static ram industrial and commercial temperature ra nges 14 notes: 1. port-to-port delay through ram cells from writing port to reading port, refer to "timing waveform of write with port-to-port read and busy (m/ s = v ih )". 2. to ensure that the earlier of the two ports wins. 3. t bdd is a calculated parameter and is the greater of the max. spec, t wdd ? t wp (actual), or t ddd ? t dw (actual). 4. to ensure that the write cycle is inhibited on port "b" during contention on port "a". 5. to ensure that a write cycle is completed on port "b" after contention on port "a". 7 ' 1a ' 1 &
,0
23 + symbol parameter 70v639s10 com'l only 70v639s12 com'l & ind 70v639s15 com'l & ind unit min. max. min. max. min. max. busy timing (m/ s =v ih ) t baa busy access time from address match ____ 10 ____ 12 ____ 15 ns t bda busy disable time from address not matched ____ 10 ____ 12 ____ 15 ns t bac busy access time from chip enable low ____ 10 ____ 12 ____ 15 ns t bdc busy disable time from chip enable high ____ 10 ____ 12 ____ 15 ns t aps arbitration priority set-up time (2 ) 5 ____ 5 ____ 5 ____ ns t bdd busy disable to valid data (3 ) ____ 10 ____ 12 ____ 15 ns t wh write hold after busy (5 ) 8 ____ 10 ____ 12 ____ ns busy timing (m/ s =v il ) t wb busy input to write (4 ) 0 ____ 0 ____ 0 ____ ns t wh write hold after busy (5 ) 8 ____ 10 ____ 12 ____ ns port-to-port delay timing t wdd write pulse to data delay (1 ) ____ 22 ____ 25 ____ 30 ns t ddd write data valid to read data delay (1 ) ____ 20 ____ 22 ____ 25 ns 5621 tbl 14
idt70v639s preliminary high-speed 3.3v 128k x 18 asynchronous dual-port static ram industrial and commercial temperature ra nges 15 &.a. 4 ' c c +,, busy 8- s : 3 )= " !6" &.a. 4 ' busy 8- s :3 )? " notes: 1. t wh must be met for both busy input (slave) and output (master). 2. busy is asserted on port "b" blocking r/ w "b" , until busy "b" goes high. 3. t wb is only for the 'slave' version. notes: 1. to ensure that the earlier of the two ports wins. t aps is ignored for m/ s = v il (slave). 2. ce l = ce r = v il . 3. oe = v il for the reading port. 4. if m/ s = v il (slave), busy is an input. then for this example busy "a" = v ih and busy "b" input is shown above. 5. all timing is the same for left and right ports. port "a" may be either the left or right port. port "b" is the port opposite from port "a". 5621 drw 12 t dw t aps addr "a" t wc data out "b" match t wp r/ w "a" data in "a" addr "b" t dh valid (1) match busy "b" t bda valid t bdd t ddd (3) t wdd t baa . 5621 drw 13 r/ w "a" busy "b" t wb (3) r/ w "b" t wh (1) (2) t wp
idt70v639s preliminary high-speed 3.3v 128k x 18 asynchronous dual-port static ram industrial and commercial temperature ra nges 16 7 ' 1a ' 1 &
,0
23 + .a busy 7( ,(2 ce & 8- s :3 )= " " .a busy 7( 2 ,(27,,8 ' & 8- s :3 )= " " notes: 1. all timing is the same for left and right ports. port ? a ? may be either the left or right port. port ? b ? is the port opposite from port ? a ? . 2. if t aps is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted. 5621 drw 14 addr "a" and "b" addresses match ce "a" ce "b" busy "b" t aps t bac t bdc (2) 5621 drw 15 addr "a" address "n" addr "b" busy "b" t aps t baa t bda (2) matching address "n" 70v639s10 com'l only 70v639s12 com'l & ind 70v639s15 com'l & ind symbol parameter min. max. min. max. min. max. unit interrupt timing t as address set-up time 0 ____ 0 ____ 0 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ ns t ins interrupt set time ____ 10 ____ 12 ____ 15 ns t inr interrupt reset time ____ 10 ____ 12 ____ 15 ns 5621 tbl 15
idt70v639s preliminary high-speed 3.3v 128k x 18 asynchronous dual-port static ram industrial and commercial temperature ra nges 17 &
'&()))*)
!" .a)
& " notes: 1. all timing is the same for left and right ports. port ? a ? may be either the left or right port. port ? b ? is the port opposite from port ? a ? . 2. refer to interrupt truth table. 3. timing depends on which enable signal ( ce or r/ w ) is asserted last. 4. timing depends on which enable signal ( ce or r/ w ) is de-asserted first. notes: 1. assumes busy l = busy r =v ih . 2. if busy l = v il , then no change. 3. if busy r = v il , then no change. 4. int l and int r must be initialized at power-up. 5621 drw 16 addr "a" interrupt set address ce "a" r/ w "a" t as t wc t wr (3) (4) t ins (3) int "b" (2) 5621 drw 17 addr "b" interrupt clear address ce "b" oe "b" t as t rc (3) t inr (3) int "b" (2) left port right port function r/ w l ce l oe l a 16l -a 0l int l r/ w r ce r oe r a 16r -a 0r int r l l x 1ffff xxxx x l (2) set right int r flag x x x x x x l l 1ffff h (3) reset right int r flag xxx x l (3) l l x 1fffe x set left int l flag x l l 1fffe h (2) x x x x x reset left int l flag 5621 tbl 16
idt70v639s preliminary high-speed 3.3v 128k x 18 asynchronous dual-port static ram industrial and commercial temperature ra nges 18
the idt70v639 provides two ports with separate control, address and i/o pins that permit independent access for reads or writes to any location in memory. the idt70v639 has an automatic power down feature controlled by ce . the ce 0 and ce 1 control the on-chip power down circuitry that permits the respective port to go into a standby mode when not selected ( ce = high). when a port is enabled, access to the entire memory array is permitted. )
if the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. the left port interrupt flag ( int l ) is asserted when the right port writes to memory location 3fffe (hex), where a write is defined as ce r = r/ w r = v il per the truth table. the left port clears the interrupt through access of address location 3fffe when ce l = oe l = v il , r/ w is a "don't care". likewise, the right port interrupt flag ( int r ) is asserted when the left port writes to memory location 3ffff (hex) and to clear the interrupt flag ( int r ), the right port must read the memory location 3ffff. the message (18 bits) at 3fffe or 3ffff is user-defined since it is an addressable sram location. if the interrupt function is not used, address locations 3fffe and 3ffff are not used as mail boxes, but as part of the random access memory. refer to truth table iii for the interrupt operation. &
'&()3* 7,, busy 7( notes: 1. pins busy l and busy r are both outputs when the part is configured as a master. both are inputs when configured as a slave. busy outputs on the idt70v639 are push-pull, not open drain outputs. on slaves the busy input internally inhibits writes. 2. "l" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "h" if the inputs to the opposite port became stable after the address and enable inputs of this port. if t aps is not met, either busy l or busy r = low will result. busy l and busy r outputs can not be low simultaneously. 3. writes to the left port are internally ignored when busy l outputs are driving low regardless of actual logic level on the pin. writes to the right port are internally ignored when busy r outputs are driving low regardless of actual logic level on the pin. &
'&(3*90'
0e
" notes: 1. this table denotes a sequence of events for only one of the eight semaphores on the idt70v639. 2. there are eight semaphore flags written to via i/o 0 and read from all i/o's (i/o 0 -i/o 17 ). these eight semaphores are addressed by a 0 - a 2 . 3. ce = v ih , sem = v il to access the semaphores. refer to the semaphore read/write control truth table. inputs outputs function ce l ce r a ol -a 16l a or -a 16r busy l (1 ) busy r (1 ) xxno match h h normal hxmatchh hnormal xhmatchh hnormal l l m atch (2) (2) write inhib it (3 ) 5621 tbl 17 functions d 0 - d 17 left d 0 - d 17 right status no action 1 1 semaphore free left port writes "0" to semaphore 0 1 left port has semaphore token right port writes "0" to semaphore 0 1 no change. right side has no write access to semaphore left port writes "1" to semaphore 1 0 right port obtains semaphore token left port writes "0" to semaphore 1 0 no change. left port has no write access to semaphore right port writes "1" to semaphore 0 1 left port obtains semaphore token left port writes "1" to semaphore 1 1 semaphore free right port writes "0" to semaphore 1 0 right port has semaphore token right port writes "1" to semaphore 1 1 semaphore free left port writes "0" to semaphore 0 1 left port has semaphore token left port writes "1" to semaphore 1 1 semaphore free 5621 tbl 18
idt70v639s preliminary high-speed 3.3v 128k x 18 asynchronous dual-port static ram industrial and commercial temperature ra nges 19
2? busy logic provides a hardware indication that both ports of the ram have accessed the same location at the same time. it also allows one of the two accesses to proceed and signals the other side that the ram is ? busy ? . the busy pin can then be used to stall the access until the operation on the other side is completed. if a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. the use of busy logic is not required or desirable for all applications. in some cases it may be useful to logically or the busy outputs together and use any busy indication as an interrupt source to flag the event of an illegal or illogical operation. if the write inhibit function of busy logic is not desirable, the busy logic can be disabled by placing the part in slave mode with the m/ s pin. once in slave mode the busy pin operates solely as a write inhibit input pin. normal operation can be programmed by tying the busy pins high. if desired, unintended write operations can be prevented to a port by tying the busy pin for that port low. the busy outputs on the idt70v639 ram in master mode, are push-pull type outputs and do not require pull up resistors to operate. if these rams are being expanded in depth, then the busy indication for the resulting array requires the use of an external and gate. address signals only. it ignores whether an access is a read or write. in a master/slave array, both address and chip enable must be valid long enough for a busy flag to be output from the master before the actual write pulse can be initiated with the r/ w signal. failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. 0' the idt70v639 is an extremely fast dual-port 128k x 18 cmos static ram with an additional 8 address locations dedicated to binary semaphore flags. these flags allow either processor on the left or right side of the dual-port ram to claim a privilege over the other processor for functions defined by the system designer ? s software. as an ex- ample, the semaphore can be used by one processor to inhibit the other from accessing a portion of the dual-port ram or any other shared resource. the dual-port ram features a fast access time, with both ports being completely independent of each other. this means that the activity on the left port in no way slows the access time of the right port. both ports are identical in function to standard cmos static ram and can be read from or written to at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous read/write of, a non-semaphore location. semaphores are pro- tected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the dual-port ram. these devices have an automatic power-down feature controlled by ce , the dual-port ram enable, and sem , the semaphore enable. the ce and sem pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. systems which can best use the idt70v639 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. these systems can benefit from a performance increase offered by the idt70v639s hardware semaphores, which provide a lockout mechanism without requiring complex programming. software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. the idt70v639 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. an advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. this can prove to be a major advantage in very high-speed systems. =4 '0' . the semaphore logic is a set of eight latches which are indepen- dent of the dual-port ram. these latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. the semaphores provide a hardware assist for a use assignment method called ? token passing allocation. ? in this method, the state of a semaphore latch is used as a token indicating that a shared resource is in use. if the left processor wants to use this resource, it requests the token by setting the latch. this processor then ., '94 '
2? 8 -0a72 when expanding an idt70v639 ram array in width while using busy logic, one master part is used to decide which side of the rams array will receive a busy indication, and to output that indication. any number of slaves to be addressed in the same address range as the master use the busy signal as a write inhibit signal. thus on the idt70v639 ram the busy pin is an output if the part is used as a master (m/ s pin = v ih ), and the busy pin is an input if the part used as a slave (m/ s pin = v il ) as shown in figure 3. if two or more master parts were used when expanding in width, a split decision could result with one master indicating busy on one side of the array and another master indicating busy on one other side of the array. this would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. the busy arbitration on a master is based on the chip enable and figure 3. busy and chip enable routing for both width and depth expansion with idt70v639 rams. 5621 drw 18 master dual port ram busy r ce 0 master dual port ram busy r slave dual port ram busy r slave dual port ram busy r ce 1 ce 1 ce 0 a 17 busy l busy l busy l busy l .
idt70v639s preliminary high-speed 3.3v 128k x 18 asynchronous dual-port static ram industrial and commercial temperature ra nges 20 verifies its success in setting the latch by reading it. if it was successful, it proceeds to assume control over the shared resource. if it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. the left processor can then either repeatedly request that semaphore ? s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. once the right side has relinquished the token, the left side should succeed in gaining control. the semaphore flags are active low. a token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. the eight semaphore flags reside within the idt70v639 in a separate memory space from the dual-port ram. this address space is accessed by placing a low input on the sem pin (which acts as a chip select for the semaphore flags) and using the other control pins (address, ce , r/ w and lb / ub ) as they would be used in accessing a standard static ram. each of the flags has a unique address which can be accessed by either side through address pins a 0 ? a 2 . when accessing the semaphores, none of the other address pins has any effect. when writing to a semaphore, only data pin d 0 is used. if a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see truth table v). that semaphore can now only be modified by the side showing the zero. when a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. the fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (a thor- ough discussion on the use of this feature follows shortly.) a zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. when a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. the read value is latched into one side ? s output register when that side's semaphore, byte select ( sem , lb / ub ) and output enable ( oe ) signals go active. this serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. because of this latch, a repeated read of a semaphore in a test loop must cause either signal ( sem or oe ) to go inactive or the output will never change. however, during reads lb and ub function only as an output for semaphore. they do not have any influence on the semaphore control logic. a sequence write/read must be used by the semaphore in order to guarantee that no system level contention will occur. a processor requests access to shared resources by attempting to write a zero into a semaphore location. if the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see table v). as an example, assume a processor writes a zero to the left port at a free semaphore location. on a subsequent read, the processor will verify that it has written success- fully to that location and will assume control over the resource in question. meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. had a sequence of read/write been used instead, system contention problems could have occurred during the gap between the read and write cycles. it is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. the reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in figure 4. two sema- phore request latches feed into a semaphore flag. whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag low and the other side high. this condition will continue until a one is written to the same semaphore request latch. should the other side ? s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side ? s request latch. the second side ? s flag will now stay low until its semaphore request latch is written to a one. from this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. the critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. the semaphore logic is specially designed to resolve this problem. if simultaneous requests are made, the logic guarantees that only one side receives the token. if one side is earlier than the other in making the request, the first side to make the request will receive the token. if both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. one caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. as with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. since any sema- phore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. figure 4. idt70v639 semaphore logic d 5621 drw 19 0 d q write d 0 d q write semaphore request flip flop semaphore request flip flop lport rport semaphore read semaphore read
idt70v639s preliminary high-speed 3.3v 128k x 18 asynchronous dual-port static ram industrial and commercial temperature ra nges 21 &7f7 ' !" symbol parameter min. max. units t jcyc jtag clock input period 100 ____ ns t jch jtag clock high 40 ____ ns t jcl jtag clock low 40 ____ ns t jr jtag clock rise time ____ 3 (1 ) ns t jf jtag clock fall time ____ 3 (1 ) ns t jrst jtag reset 50 ____ ns t jrsr jtag reset recovery 50 ____ ns t jcd jtag data output ____ 25 ns t jdc jtag data output hold 0 ____ ns t js jtag setup 15 ____ ns t jh jtag hold 15 ____ ns 5621 tbl 19 notes: 1. guaranteed by design. 2. 30pf loading on external output signals. 3. refer to ac electrical test conditions stated earlier in this document. 4. jtag operations occur at one speed (10mhz). the base device may run at any speed specified in this datasheet. &7f&0 tck device inputs (1) / tdi/tms device outputs (2) / tdo trst t jcd t jdc t jrst t js t jh t jcyc t jrsr t jf t jcl t jr t jch 5621 drw 20 x notes: 1. device inputs = all device inputs except tdi, tms, and trst. 2. device outputs = all device outputs except tdo.
idt70v639s preliminary high-speed 3.3v 128k x 18 asynchronous dual-port static ram industrial and commercial temperature ra nges 22 ), + instruction field value description revision number (31:28) 0x0 reserved for version number idt device id (27:12) 0x30c defines idt part number idt jedec id (11:1) 0x33 allows unique identification of device vendor as idt id register indicator bit (bit 0) 1 indicates the presence of an id register 5621 tbl 20 0+ 0g register name bit size instruction (ir) 4 bypass (byr) 1 identification (idr) 32 boundary scan (bsr) note (3) 5621 tbl 21 02 ) instruction code description extest 0000 forces contents of the boundary scan cells onto the device outputs (1 ) . places the boundary scan register (bsr) between tdi and tdo. b ypa ss 1111 p lac e s the b y p as s re g i s te r (b yr) b e twe e n tdi and tdo. idcode 0010 loads the id register (idr) with the vendor id code and places the register between tdi and tdo. highz 0100 places the bypass register (byr) between tdi and tdo. forces all device output drivers to a high-z state. clamp 0011 uses byr. forces contents of the boundary scan cells onto the device outputs. places the bypass register (byr) between tdi and tdo. sample/preload 0001 places the boundary scan registe r (bsr) between tdi and tdo. sample allows data from device inputs (2 ) and outputs (1 ) to be captured in the boundary scan cells and shifted serially through tdo. preload allows data to be input serially into the boundary scan cells via the tdi. reserved all other codes several combinations are reserved. do not use codes other than those identified above. 5621 tbl 22 notes: 1. device outputs = all device outputs except tdo. 2. device inputs = all device inputs except tdi, tms, and trst . 3. the boundary scan descriptive language (bsdl) file for this device is available on the idt website (www.idt.com), or by conta cting your local idt sales representative.
idt70v639s preliminary high-speed 3.3v 128k x 18 asynchronous dual-port static ram industrial and commercial temperature ra nges 23 1,) 5621 drw 21 a power 999 speed a package a process/ temperature range blank i commercial (0 cto+70 c) industrial (-40 cto+85 c) bf prf bc 208-ball fpbga (bf-208) 128-pin tqfp (pk-128) 256-ball bga (bc-256) 10 12 15 s standard power xxxxx device type 2304k (128k x 18) asynchronous dual-port ram 70v639 idt speed in nanoseconds commercial only commercial & industrial commercial & industrial the idt logo is a registered trademark of integrated device technology, inc. corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 831-754-4613 santa clara, ca 95054 fax: 408-492-8674 dualporthelp@idt.com www.idt.com 2 ' h definition "preliminary' datasheets contain descriptions for products that are in early release. '
= 2h 6/1/00: initial public offering. 8/7/00: pages 6,13,20 inserted additional lb and ub information. 6/20/01: added jtag information for tqfp package on page 1. increased busy timing parameters t bda ,t bac ,t bdc and t bdd for all speeds on page 14. changed maximum value for jtag ac electrical characteristics for t jcd from 20ns to 25ns on page 21.

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